The search for a processor - MPW and chipIgnite - page 2



-x-x-x-

####### Tuesday 18 July 2023 10:31:40 PM IST #######
88.
Hammer VLSI flow - supported in Chipyard


####### Tuesday 18 July 2023 06:59:25 PM IST #######
- said to be fast
- can boot linux and ssh into the sim (cool !)


latest workshop (march 2023):
TODO: watch all of them
https://fires.im/workshop-2023/
- videos on a wide array of topics

FireSim + Chipyard tutorial
https://fires.im/asplos-2023-tutorial/

Chipyard 
https://www.youtube.com/watch?v=EXbs5VSv19c
- chipyard basics
- chipyard + firesim --> tutorial step-by-step

Firesim Tutorial - with AWS F1 instances
https://www.youtube.com/watch?v=VOcSpfM7KXk
- firesim capabilities showcase / overview
- large scale simulation on cloud
- local hardware
- orchestration - for setting-up the simulation infra as well
- well integrated with chipyard 


####### Tuesday 18 July 2023 05:09:39 PM IST #######
- for intra-chip interconnect
- operation priority design is completely ascending - ensuring that there is no blocking for a single operation
- loops are not allowed in the topology graph 

TileLink Uncached Lightweight (TL-UL) 
- supports only simple memory read and write (Get/Put) operations of single words. 

The next most complex is TileLink Uncached Heavyweight (TL-UH),
- which adds various hints, atomic operations, and burst accesses but without support for coherent caches.

Finally, TileLink Cached (TL-C)
- is the complete protocol, which supports use of coherent caches.


Chip Link
- https://doc-en.rvspace.org/JH7100/Datasheet/JH7100_DS/chiplink.html
- scifive proprietery implementation of the tile link protocol for off-chip application:

OmniXtend
- tile link implementation over networking protocol - ethernet if I am not wrong
- can share cache coherent memory across a long graph - even with offchip memory
https://github.com/chipsalliance/omnixtend
https://www.youtube.com/watch?v=5Ax-qxK3fxE
- motivation: datacenter + AI / ML accelerators with cache coherent memory 
Demo with Xilinx 
https://www.youtube.com/watch?v=hmVNTUrJoDM

here capability discovery would be an issue when hot-wiring chips / components / actors / nodes


####### Tuesday 18 July 2023 04:47:14 PM IST #######
91.
Cache Coherence

https://www.youtube.com/watch?v=r_ZE1XVT8Ao
- snooping and directory based protocols introduction

https://www.youtube.com/watch?v=YNpaELJZm2c
- Snooping based protocols details 

- Directory based protocols

-x-x-x-x-
although his hello !! is a bit over the top, the animations and explanations are on point.




####### Monday 03 July 2023 08:40:44 PM IST #######
92.
Debugging with OpenLane and OpenRoad


- GUI to visualize the layout and colour coded params - to identify potential problem areas quickly


####### Monday 03 July 2023 08:23:51 PM IST #######
93.
Wishbone bus demo with the Caravel base wrapper 
- demo of connections
- test-bench setup and run
- and viewing the states of the pins / buses through the run


self-describing wishbone bus:
https://av.tib.eu/media/40048
- pretty generic
- good framework for auto discovery


####### Monday 06 March 2023 09:54:25 PM IST #######
94.
Building riscduino 

- clone repo


next steps section as suggested in the video above
- rename origin name from original author to upstream (secondary upstream, mostly for getting latest code and sending pull requests)
- add own repo link as origin (primary upstream)

git clone git@github.com:sanyamsmulay/riscduino.git
cd riscduino
git submodule init 
git submodule update 


next steps section as suggested in the documentation above

    make setup

--> should build everything
BUT
-x-x-x-
- this did not work out of the box.. needs fixing - (it has become out of date)
- that quoted branches / tags for mpw9 and other do not exist.. 
- docker images do not exist anymore
- fixed  the docker image, but seems like everything is outdated.
- openlane make step for sky130-pdk failing 
- trying to find a version of openlane where the make for the sky130-pdk is running
- currently conda.cli was not found
- pointing the openlane to tag:2023.03.08
- fixed in my clone:
master branch of my fork - 
git@github.com:sanyamsmulay/riscduino.git

- tried running the tests / simulations
- basic wishbone check in caravel did not run on the docker image provided for iverilog
error: 
iverilog sorry: constant selects in always_* processes are not currently supported 
(all bits will be included)

- did not get a suitable resolution to it
- tried all the generation flags available - the error does not change
- assuming a fresh build of iverilog would be able to run this
- built iverilog from source
- iverilog - local build needs glibc --> 2.34 
iverilog/bin/iveriloglocal_install: /lib/x86_64-linux-gnu/libc.so.6: 
version `GLIBC_2.34' not found
https://superuser.com/a/537694 --> talks about the above error
https://superuser.com/questions/537683/how-to-fix-lib-x86-64-linux-gnu-libc-so-6-version-glibc-2-14-not-found --> other interesting solutions on the thread 

- building glibc from source
guide: https://www.linuxfromscratch.org/lfs/view/11.0/chapter08/glibc.html
code: https://www.linuxfromscratch.org/lfs/view/11.0/chapter03/packages.html
patch: https://www.linuxfromscratch.org/patches/lfs/11.0/glibc-2.34-fhs-1.patch  (to be applied to code after download)
pre-built: (https://launchpad.net/ubuntu/+source/glibc/2.34-0ubuntu2)
will try this next if the build from source does not work

- asm needs to have correct header files
https://stackoverflow.com/a/26473181 (idea for symbolic link from this post)
how to find which directory to link: https://gist.github.com/gut/f1554ded7671af4e6e58
hint: search dpkg for the header file prctl.h and link the appropriate one
- was already installed: linux-libc-dev
sudo ln -s /usr/include/x86_64-linux-gnu/asm /usr/include/asm 

- error building glibc from source:
/usr/bin/ld: /usr/lib/gcc/x86_64-linux-gnu/11/../../../x86_64-linux-gnu/libgcc_s.so.1: undefined reference to `_dl_find_object@GLIBC_2.35'
collect2: error: ld returned 1 exit status
https://stackoverflow.com/a/39703556 (gave the idea for trying to do a clean install)
so that artefacts from the failed steps do not affect the build


#### Tuesday 21 February 2023 09:57:20 PM IST #######
95.
Riscduino
https://github.com/dineshannayya/riscduino
- multi-core risc-v
- arduino compatible pin out - to a large extent
- wishbone bus 

this is the best starter I could find for building a risc-v arduino board.


more about riscduino
repo: https://github.com/dineshannayya/riscduino
- documentation is great
intro video by the maintainer: https://www.youtube.com/watch?v=lFVnicPhTI0

arduino IDE / sketch definitions for connecting to and programming the PCB
https://github.com/dineshannayya/riscduino_board


build steps description:
https://theopenroadproject.org/implementation-of-riscduino-core-using-a-hierarchical-design-flow/
- build using openROAD and OpenLane
- uses hierarchical design
- very useful tips / thumb rules in the article:
group similar blocks - fragmented floorplan makes top-level timing closure difficult

logically partitioning the blocks - makes faster RTL-GDSII runtime and timing clusure easy


manual macro pin placement - gives better global routing (one way of saying the project id not good enough to auto route :P)
OpenROAD can give a preview for macro-connectivity, Eg:


Feedthrough partition to connect blocks to top-level i/o - for congestion-free routing
Eg.
block level SDC, slightly tighter than the overall available -  at macro ports
thumb rule: Allocate: 60% for external delay with 40% total for block + 20% interconnect. Hold delay constraints: 1ns External delay


run timing at top-level first,
if with the above thumb-rule, there are violations at the top, make room in the macro/lower level constraints, make sure the macro is not violating the lower margins and run again for top level.


quoting from the article:
Flow Summary

Here is a summary of the flow steps:

  1. Design Partitioning
  2. Time budgeting and defining initial constraints
  3. Floorplanning
    1. Macro placement and feedthroughs
    2. Fine tuning SDC constraints
    3. Power network generation
  4. Clock tree synthesis at top-level
    1. Balance clock skew
    2. Add repeaters as needed
  5. Harden each Macro RTL-GDSII implementation in OpenLane
  6. Top-level integration
    1. Hooking up Macros to top-level
  7. Chip-level signoff
    1. Load verilog files for all levels of hierarchy
    2. Load Macro & Top-level SPEF files
    3. Run top-level, flat timing analysis for all three corner
    4. Make sure that there are no hold violations in 9 corners –Library (Fast/Typical/Slow) Vs Spef (Max/Nom/Min)
    5. Analysis the Max timing margin for each clock domain across each corner.
thicker and more frequent power lines -
 


each macro has a adjustable skew adjust:



impressive design results:
- 150K cells + 48 Kb SRAM (from sky130 pdk) 
- fmax of 100Mhz.


Figure below shows the final routed GDSII for the RISCduino Score, Dcore and QCore designs.




this article taught me more in 1 hour than any course ever did.


####### Wednesday 15 February 2023 08:24:19 PM IST #######
96.
efabless: components marketplace for ASIC design:
https://platform.efabless.com/design_catalog/info


### Wednesday 08 February 2023 11:23:23 PM IST #######
97.
How to build for the MPW-6 (should be similar for other shuttles I think)
https://www.youtube.com/watch?v=MNuoYz_MM-c

####### Wednesday 08 February 2023 11:18:29 PM IST #######
98.
The next Open MPW shuttle ?
- not getting any info 
- may be just go for the chipIgnite -12 June 2023


###### Wednesday 08 February 2023 11:08:45 PM IST #######
99.
riscduino - is based on the caravel base chip template
https://github.com/dineshannayya/riscduino

more about it on #95.

 ####### Wednesday 08 February 2023 10:57:53 PM IST #######
100.
https://www.youtube.com/watch?v=vJqP7ZR0NrI
Open MPW 
- google sponsored shuttle

chipIgnite
- 9725 USD
- for:
-- 300 WCSP OR -- 100 QFN - 
-- 5 evaluation boards


caravel base chip
- https://github.com/efabless/caravel
- management area + user project area
- 10mm sq user area
- management area - good base functionality (very tightly packed ! )
- some genius features of the management SoC
-- access to SPI of the user area SPI as slave - can be used for configuring at runtime (eg. the guitar string project)
-- access to user area wishbone as master (can check if rest of the chip is working well or not )
-- protection from user area on the wishbone bus

-NOICE !



this a good starter for a chip in-itself.


Steps for building for an open mpw shuttle

- Integrate design into the caravel user wrapper
- verify the HDL integration
- Harden Design
- submission pre-check
- submit for tapeout 



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