The search for a processor - page 1



-x-x-x-

####### Wednesday 09 August 2023 11:59:34 PM IST #######
20.
Other parts of the value chain companies

- 
IIT Bombay - guy working on the supply chain, finance and other aspects of the semi-conductor ecosystem.



####### Wednesday 05 July 2023 01:16:21 AM IST #######
21.
India Gov Fab facility 

8 inch 
180nm 
CMOS


####### Tuesday 04 July 2023 02:24:20 PM IST #######
22.
Semicon India - Future Design Roadshow
- 24th Feb 2023
https://www.youtube.com/watch?v=X4b8x5NGh6c

####### Saturday 04 March 2023 08:12:47 PM IST #######
23.
Finally found out where the shakti team went, been looking for them for a while now:


- cromite core 

#### Sunday 26 February 2023 05:29:47 PM IST #######
24.
Fastest RiscV processors -
https://scifilogic.com/most-powerful-risc-v-processor/


#### Sunday 26 February 2023 05:24:13 PM IST #######
25.
Good maintainer of software for risc-v linux - Vision five
- 


####### Wednesday 15 February 2023 08:28:21 PM IST #######
- good inspiration for designs


####### Monday 13 February 2023 12:07:41 AM IST #######
27.

- make sure that after any customization - the value chain, compilers, OS-es, etc don't break due it and there is backward compatibility (Eg. the same things/operations can be done, but may take longer, or be less precise if done without the extension being present on the basic chip )

#### Friday 10 February 2023 12:02:10 AM IST #######
28.
LiteX - ecosystem
https://anaconda.org/LiteX-Hub - 
https://github.com/proppy/conda-eda - Conda recipes for FPGA EDA tools

####### Thursday 09 February 2023 11:57:36 PM IST #######
29.
XSchem - schematic design tool for custom designs
https://github.com/StefanSchippers/xschem
- available sim backends - VHDL, Spice, Verilog
- good keyboard shortcuts and good workflow with a mouse and a keyboard
tutorials from the creator of the lib:
https://www.youtube.com/@stefsport2002/search?query=xschem

- https://www.youtube.com/watch?v=KgBLByOkJxA
- non-trivial example 


####### Wednesday 08 February 2023 10:21:18 PM IST #######
30.
this is the kind ecosystem one needs to build for a chip to be successful
https://www.pine64.org/pinenote/

- the hardware is open source
- there need to be a lot of sample projects around a chip that can act as starters for others to develop.
- right up to the PCB 
- so that with minor modifications people can kick off their projects
- although the chip is not open source

https://www.tomshardware.com/news/risc-v-10-usd-development-board
about the project:

####### Wednesday 01 February 2023 09:16:48 PM IST #######
31.
efabless - has many peripheral ips in their chip builder 
- Eg. ADCs, DACs etc !!
https://efabless.com/


####### Wednesday 01 February 2023 08:50:16 PM IST #######
32.
250 nm process nodes made - Intel Pentium processors 
- so this can be a good node size to start with to build the first set of ICs

####### Wednesday 01 February 2023 08:50:21 PM IST #######
33.
Great idea / usecase for custom silicon - custom motor driver circuitry:
https://www.youtube.com/watch?v=gE_xAmWi_YQ

- on these lines - these guys can be first clients for my processor :)
https://www.thebetterindia.com/309314/bengaluru-deep-tech-startup-chara-builds-rare-earth-metal-free-electric-vehicle-motors/


####### Tuesday 31 January 2023 08:25:57 PM IST #######
34.
Blinky - LED blinking examples for all the FPGA dev boards in the world
https://github.com/fusesoc/blinky


####### Monday 30 January 2023 07:09:34 PM IST #######
35.
HDL options:

SpinalHDL - Scala based HDL
myhdl - The MyHDL development repository
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
bsc - Bluespec Compiler (BSC)
circt - Circuit IR Compilers and Tools
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
pygears - HW Design: A Functional Approach
chiseltest - The official testing library for Chisel circuits.
chiselverify - A dynamic verification library for Chisel.


####### Monday 30 January 2023 07:02:49 PM IST #######
36.
My sheet for listing tools 
https://docs.google.com/spreadsheets/d/1RQ0_Qu-0O7UnnXXzLmw8ttM7VG0Ag2sm6gmFpO3FV2s/edit#gid=1853968626

####### Monday 30 January 2023 05:03:53 PM IST #######
37.
AWS - FPGS instances - 
https://aws.amazon.com/ec2/instance-types/f1/

###### Monday 30 January 2023 04:26:23 PM IST #######
38.
More cores:

VROOM - core
https://github.com/MoonbaseOtago/vroom

- it seems all the right extensions for making a server class 


####### Tuesday 31 January 2023 07:43:56 PM IST #######
blackparrot core 
- https://github.com/black-parrot/black-parrot

femtorv core
- quark (RV32I), electron (RV32IM), intermissum (RV32IM + irq), gracilis (RV32IMC + irq), petitbateau (RV32IMFC + irq)
- experimental for teaching and focus on being tiny so as to fit on inexpensive fpgas

SERV core
- word's smallest risc-v cpu
- can run zephyr OS
- maintainer olofk - (I follow him on twitter)
- interesting design option when a small CPU would be a good idea
https://diode.zone/w/0230a518-e207-4cf6-b5e2-69cc09411013


biRISC core
- 32 bit - dual issue - hence the bi- I suppose
- in-order 6-7 stage pipeline
- linux capable 
- compares to ARM7, Scifive E76


IceV core
- written in slice 
- small core for teaching
- 


Lattice Micro
LM32 core 
https://github.com/m-labs/lm32/

- very old core - not updated in 7-8 years


NeoRV32 core
https://github.com/stnolting/neorv32
- core and SoC 
- micro-controller scale


Glacial core 
https://github.com/brouhaha/glacial
- very non standard 
- but can run the Zephyr OS kernel

or1k_marocchino
https://github.com/openrisc/or1k_marocchino
- fairly mature core
- out-of-order implementation 



NaxRiscv core
https://github.com/SpinalHDL/NaxRiscv
- out of order execution
- (RV32/RV64)IMAFDCSU (Linux / Buildroot works on hardware)
- comparable to ARM4
- seems like a mature project
- 

####### Saturday 04 February 2023 12:40:34 PM IST #######
steel core
https://github.com/rafaelcalcada/steel-core
- for embedded applications
- 3 stage

quasiSoC
https://github.com/regymm/quasiSoC


####### Wednesday 18 January 2023 07:37:26 PM IST #######
39.
Adani's first silicon ingot - it is solar panel class
https://www.youtube.com/watch?v=AFF4Jvoo4d8

- soon !

####### Saturday 03 December 2022 09:09:56 PM IST #######

40.
The history and story of Lithography:
https://www.youtube.com/watch?v=SB8qIO6Ti_M
- Nikkon and Canon had 85% market share and were still beaten by ASML
- when tech shifted from visible light to EVU etc




41.
ASML - Advanced Semiconductor Material Lithography
Compared to #42
https://www.youtube.com/watch?v=IS5ycm7VfXg

- makes the most advanced "chip printers"
- the only supplier of EUV machines in the universe :D
- was a subsidiary of Philips !!!!
- a very complicated and inter connected ecosystem
- the network ASML has built is it's biggest defence



DUV machines are more easily available as compared to EUV






42.
This guy is an absolute legend:
https://www.youtube.com/watch?v=IS5ycm7VfXg
- fabricating integrated circuits in his garage

Another legend:
https://www.youtube.com/watch?v=KzSaFFpBPDM
- complete RISC-V32I instruction set




####### Saturday 03 December 2022 08:58:53 PM IST #######
43.
Annapurna Labs
https://en.wikipedia.org/wiki/Annapurna_Labs


Israeli chip design startup bought by Amazon for 350 million USD




####### Friday 02 December 2022 02:44:20 PM IST #######
44.
How AMD caught-up to Intel
https://www.youtube.com/watch?v=_gLm0Jo0cnk
- history of the two companies
- :D "real men have fabs"
- fab business and chip design business are fundamentally different
-- different business cycles
-- different cap-ex and op-ex requirements

- by separating the two and and a Hail Mary product innovation - Zen architecture.. AMD just flourished.




45.
Advances in chip technology:
https://www.youtube.com/watch?v=VsUF_CBJq50

# Neuromorphic chips:
- chips that mimic a neural connections



# potonic connections for faster and lower energy sub-system communication (may be in the future all connections will be photonic) - essentially depends how cheaply electrons and photons can be interconvertible. This number will dictate how long the connection needs to be for photonics to be lower energy that a wire connection.
Eg. trans-Atlantic cables are already light based.

# carbon nano-tube based transistors
- much lower resistance




46.
10th Nov 2022
The space is heating up.
ISMC - mysuru plan get investments from Reliance and HCL
https://economictimes.indiatimes.com/tech/technology/reliance-hcl-may-enter-indian-semiconductor-race-exploring-a-stake-in-ismc/articleshow/95364243.cms?from=mdr




47.
Looking for a FPGA board to start building a prototype:
https://www.electronicshub.org/best-fpga-development-boards/

- one of the best boards since it is
https://www.hackster.io/news/ulx3s-is-a-robust-open-source-lattice-fpga-development-board-326aa28becbd

(Bought this !! Arrived: 1st Nov 2022)

48.
Cores comparison:
http://jips-k.org/full-text/326
- how the cores fare on a Xilinx Parallella Board




49.
Chinese cores - page
https://www.rvmcu.com/




50.
Some more cores (18th Oct 2022)

#
Roa Logic RV12 core 
- https://github.com/RoaLogic/RV12

#
Orca core 
https://github.com/riscveval/orca-1

#
MRISCV core - focuses no the integer extension of RISC-V
https://github.com/onchipuis/mriscv

#
Picorv32 core
https://github.com/YosysHQ/picorv32
- multiple projects using this core are linked below
- versatile and tested core


#
Humming bird core and related ecosystem
Core and SoC
https://github.com/riscv-mcu/e203_hbirdv2
Software ecosystem
https://github.com/riscv-mcu/hbird-sdk/




51.
EDA space itself is a good space with a lot of scope:
Siemens EDA (formerly Mentor Graphics)
https://semiengineering.com/entities/mentor-a-siemens-business/






52.
Sifive surges ahead !
https://www.cnx-software.com/2022/10/10/intel-horse-creek-platform-sifive-p550-risc-v-cpu-8gb-ddr5-pcie-gen5/

- will the investment from Intel prevent the emergence of a competitor


Also,
https://wiki.pine64.org/wiki/Ox64
- a board based on BL808
https://wiki.pine64.org/wiki/Ox64#SoC_and_Memory_Specification
main chip datasheet:
https://github.com/bouffalolab/bl_docs/blob/main/BL808_DS/en/BL808_DS_1.1_en.pdf
- not open source for the chip 
- but good maintainers of the software chain

53.
ASIC for micro LEDs for AR/VR headsets
https://www.kura.tech/

- micro LEDs + wave-guide eyepiece




52.
Indian CMOS image sensor designers from IITD:
https://web.iitd.ac.in/~msarkar/others.html
- teaming up with veteran manufacturer to fabricate their design
- Berkeley Skydeck - selected for the accelerator
- Indian Defence - are their first clients

https://www.cbinsights.com/company/3rditech/financials
https://www.thirditech.in/

Their pitch deck.
http://image-sensors-world.blogspot.com/2021/02/first-image-sensor-startup-in-india.html
research and papers:
https://web.iitd.ac.in/~msarkar/research.html

News: 27 Sep 2022
https://www.ga.com/ga-asi-and-3rditech-announce-joint-strategic-partnership-for-cutting-edge-semiconductor-technologies




53.
Great comparison between: Open RISC and RISC-V

https://iis-people.ee.ethz.ch/~gmichi/asocd/lecturenotes/Lecture6.pdf
(slide 38)

- What risc-v org has to say about open risc
https://riscv.org/blog/2014/10/why-not-build-on-openrisc/
- very valid
- although on the face of it (from the lecture PDF) it seems that open risc has an edge as risc-v loses clock cycles when executing branching
but that loss will become trivial if the higher compression in risc-v will start to be dominant.

So I believe that there will space for both the implementations in the future.
- OpenRisc for pipelines where branching without prefect type computing is required - (I may be naive about this, I don't know many use cases for this)
- risc-v will be dominant where code density will outweigh 2 lost clock cycles in branching

Wikipedia pages for both:
https://en.wikipedia.org/wiki/RISC-V
https://en.wikipedia.org/wiki/OpenRISC




54.
core connect vs wishbone comparison

- not much could be found in this regard
- probably will need to build the comparison on my own
https://en.wikipedia.org/wiki/Wishbone_(computer_bus)
individual bus summaries:
http://www.pldworld.com/_altera/html/_excalibur/add/ov-embeddedbusses.pdf




55.
King of the embedded development - atleast the hobbyist word
Arduino:
- the IDE
https://docs.arduino.cc/software/ide-v2
- the boards and shields:
https://docs.arduino.cc/


56.
The kings of the embedded world currently:

Atmel: (bought by microchip now)
- atmega series:

Microchip:
- PIC microcontroller series
- MPLAB -> IDE and the complete toolchain




57.
Shows, how much progress Sifive has made:
- their chip core generator:
https://www.sifive.com/core-designer
- each class of cores explained:
https://www.sifive.com/risc-v-core-ip

16th March 2022
Series F:
https://www.sifive.com/press/sifive-leadership-in-risc-v-powers-2.5b-company-valuation




58.
A complete project on a FPGA (based on the picorv32):
the talk by the maker:
https://www.youtube.com/watch?v=X39nnPWmkvA
the articles around it:
- introduction to the talk video:
https://hackaday.com/2020/02/19/machine-inside-of-a-chip-how-sprite_tm-built-the-fpga-game-boy-badge/
- Quickstart and basic hardware documentation:
https://hackaday.io/project/167255-2019-hackaday-superconference-badge
- building for FPGA board:
https://www.youtube.com/watch?v=k2rN8FE1jWM
the FPGA board is open source: https://github.com/icebreaker-fpga/icebreaker

documentation for the graphics sub-system:
TODO: go through in more detail
https://github.com/Spritetm/hadbadge2019_fpgasoc/blob/master/doc/gfx.md




59.
Standardization at the lower level of the tech stack leads it to being commoditized and gives more flexibility for the upper level:
https://hackaday.com/2021/02/27/exploring-the-open-source-that-really-goes-into-a-risc-v-chip/
https://www.youtube.com/watch?v=VdPsJW6AHqc

- probably the reason RSIC-V may succeed.

-x-x-x-

Who cares about risc-v ?
https://www2.deloitte.com/xe/en/insights/industry/technology/technology-media-and-telecom-predictions/2022/risc-v-open-source-cpu.html




60.
15th Aug 2022
Found another useful core:
https://github.com/syntacore/scr1

- one of the very complete MCU class cores
kudos to the project

- from the same project group that maintains the Zephyr OS 

-x-x-x-

Pulp core series:
https://pulp-platform.org/
the main repo:
https://github.com/pulp-platform
lecture notes from ETH Zuric:
https://iis-people.ee.ethz.ch/~gmichi/asocd/lecturenotes/Lecture6.pdf


####### Sunday 29 January 2023 07:18:21 PM IST #######
- 64-bit; 6-stage;
https://github.com/lowRISC/ariane
- with open piton - can boot linux (as of 2019)
-



- IBEX - 32-bit; 2-stage
https://github.com/lowRISC/ibex
- CVA6 is a 6-stage, 64-bit
https://github.com/openhwgroup/cva6
- CV32E40P; 32-bit, 4 stage
https://github.com/openhwgroup/cv32e40p



(21 Aug 2022)
Found a new core:
RI5CY
forked from: pulp
https://github.com/embecosm/ri5cy





One of the implementations sold commercially:
https://greenwaves-technologies.com/store/
the chip:
https://greenwaves-technologies.com/gap8_mcu_ai/
the development board:
https://greenwaves-technologies.com/product/gapuino/




-x-x-x-
16th Aug 2022

All of the open hardware cores and roadmap:
https://github.com/openhwgroup/core-v-cores




61.
Found more cores:

- Vexriscv
claimed to be FPGA friendly
https://github.com/SpinalHDL/VexRiscv
some projects based on this core:
https://www.hackster.io/matrix-labs/risc-v-soc-soft-core-w-micropython-on-matrix-voice-fpga-7be85c
- can boot linux in some supporting projects
https://github.com/SpinalHDL/SaxonSoc
- can work on ulx3s


- WARP
https://github.com/stevehoover/warp-v
- also has a generator / configurator - https://warp-v.org/
some projects with this core:
https://www.hackster.io/steve-hoover/warp-v-the-most-flexible-risc-v-cpu-core-generator-5d99e2
- has been silicon verified it seems and has been worked upon by Google summer of code students
- ok ! this is another promising generator candidate
(can try to plug it into generators that have SOC support, since this projects lacks memory and IO subsystems)
####### Sunday 29 January 2023 07:40:09 PM IST #######
- seems like it is not very complete for SoC related additions that are required


-x-x-
(21 Aug 2022)
z-scale (deprecated):
https://github.com/ucb-bar/zscale




62.
A major semi-conductor manufacturer that I did not know about up till now:

https://in.micron.com/products

- seems like the heavy weight in memory




63.
EDA tools:


Easy eda, free tool, no open source
- https://easyeda.com/page/pricing

- free and open source and free online IDE for verilog and system-verilog
https://www.edaplayground.com/home
https://github.com/edaplayground




64.
Another generator:
This is different from Chip Alliance:
https://chipyard.readthedocs.io/en/latest/Chipyard-Basics/Initial-Repo-Setup.html

- this has the rocket chip available
- and seems like a SoC generator as compared to a core generator.

Whole scope of chipyard:
https://www.youtube.com/watch?v=EXbs5VSv19c


65.
For RAM design:
https://openram.org/
- SKY130 compatible






66.
Complete chip generator:
https://github.com/chipsalliance/rocket-chip

Filing this separately from the rocket core since this one seems to be a different category of project all together.

good slides from 2015:
https://caxapa.ru/thumbs/733265/riscv-zscale-workshop-june2015.pdf
- give a good understanding of the generator architecture

- seems like the most promising point to start
but since it is in scala - dunno may the ecosystem may fail me.
jury is still out.
- supports the BOOM core as well.
- logic core + L1 cache is treated a unit.
- can go multi core easily
- some accelerators are also available

- may be a good point to start would be to have a board designed for the TV market...
since I have failed to find things that can run the android TV OS.
so say, quad core + 4GB ram + 2GB-GPU all in RISC-V




dunno if it will be worthwhile to port this to amranth, python from scala; or may be it is my bias in favour of python in comparison to scala.
cause unless there is a lot of difference is sim time and a lo of hardware is required.. then may be it would be worthwhile to port




67.
HDL simulators:

https://hackernoon.com/top-4-hdl-simulators-for-beginners
- Icarus Verilog - open source; only verilog
- GHDL - open source; only VHDL
- Vivado from Xillin - closed source; mostly targeted towards Xillin FPGAs
- Questa and Modelsim from Simens - closed source; more general prupose than Vivaldo

currently the landscape seems slightly grim here; with limited choices.
hope amaranth project has something to offer here.
TODO: revisit simulators when relevant




-x-x-x-
open source world:

- fuseSoC
https://fusesoc.readthedocs.io/en/stable/user/introduction.html
- seems promising
- good wrapper over existing tools
- from core to EDA tool



68.
Other cores I found:

- Minerva
https://github.com/minerva-cpu/minerva
- 6 stage pipeline


- Misato
https://github.com/GuzTech/misato

- Sonic BOOM - Berkeley Out-of-Order Machine
https://boom-core.org/

(in my understanding since in-order and out-of-order may or may not be faster than each other depending on the compiler / assembler / programmer being smart, planning to stick to in-order like most of the cores )
this is a good discussion:
https://stackoverflow.com/questions/24786922/difference-between-in-oder-and-out-of-order-execution-in-arm-architecture
- out of order completion seems more promising for good speed.
- will be a bit power hungry by default due the required book keeping


- rocket core:
https://chipyard.readthedocs.io/en/latest/Generators/Rocket.html








69.
Platform agnostic drivers: Interesting concept
https://github.com/rust-embedded/embedded-hal




70.
Choice of HDL - seems like there are multiple options available:

a good list can be found here:
https://en.wikipedia.org/wiki/Hardware_description_language

-x-x-x-
the relative new comers:
-x-x-x-

- amaranth - since this is a python based project - I am inclined towards this one
https://github.com/amaranth-lang/amaranth/
- seems like the most mature project of the lot
based on the:
migen project
https://m-labs.hk/gateware/migen/



- MyHDL
https://www.myhdl.org/
- claims to be silicon / FPGA proven




- PyRTL
https://ucsbarchlab.github.io/PyRTL/
- seems like a very academically oriented project

- PyMTL 3 (Mamba)
https://github.com/pymtl/pymtl3
- more complete and active as compared to PyRTL







-x-x-x-
the incumbents:
-x-x-x-



- VHDL

- VERILOG

- System Verilog







-x-x-x-
an HDL for PCBs
python project:

https://github.com/devbisme/skidl
- good set of features: https://github.com/devbisme/skidl#features
- seems to have good abstraction upon initial high-level inspection (README :D)
- can be fed to a program like KiCad's PCBNEW to create the physical PCB (line from readme)




71.
Bumblebee core and GD32V
https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
doesn't seem to be an open core






72.
The case for a RISC-V arduino type board

Does it already exist ?

- open source does not exist I guess,

- HiFive1 - Arduino RISC-V Dev Board - retired;
https://www.sparkfun.com/products/retired/15148
I am sure there is a new version planned from SciFi
- seems like it was promising, but did not last long
- touted as the fastest Arduino - The Arduino Cinque - all related google articles are ~2017




Around 2019 RevB version of the FE310 (RTL available) SoC was released:
https://www.sifive.com/blog/freedom-everywhere--back-for-everyone
(I think this is a similar idea as reliance-jio to use early users as test beds for ironing out kinks in the current core / board )


https://github.com/sifive/freedom
- the repo for the RTL has not been maintained since 1Mar2021 - the seem it has outlived the purpose of a capability showcase and has been abandoned that the business and funding has kicked off.
- also this could have been competing with the main business for funds and also for clients
- this is just speculation, and it not good to assume the worst in people, but one shouldn't be naive as well.
- but in the end it is encouraging to see rocket-chip as dependency




-x-x-x-
15th Aug 2022
- finally found something:

- does not seem to be open source though:

https://en.wikipedia.org/wiki/ESP32
core: Xtensa LX6
the family has dual and single core options
the instruction set does not seem to be standard risc
https://en.wikipedia.org/wiki/Tensilica#:~:text=The%20Xtensa%20instruction%20set%20is,and%20one%20special%2Dpurpose%20register.


Available on arduino:
https://github.com/espressif/arduino-esp32
https://espressif-docs.readthedocs-hosted.com/projects/arduino-esp32/en/latest/index.html




-x-x-x-
15th Aug 2022

this project offers pin compatibility with the arduino platform
https://www.hackster.io/ef/riscduino-dual-core-6b64a0
https://www.hackster.io/ef/riscduino-single-core-d17324


####### Tuesday 21 February 2023 10:03:32 PM IST #######
this is the most promising starter
https://github.com/dineshannayya/riscduino

more on this topic:
https://swlearninglog.blogspot.com/2023/02/the-search-for-processor-mpw-and.html#95



73.
List of all known RISC-V cores, SOCs, etc
Archived page, so a lot of info would be out of date
https://github.com/riscvarchive/riscv-cores-list




74.
performance analysis for various open source cores:
https://bitlog.it/20220118_asic_roundup_of_open_source_riscv_cpu_cores.html

- software: cadence innovus
- lot of assumptions in the analysis so the number are not really representative of the capability of the cores.


75.

Compiler assembly code for the same algo / code for various instruction sets

working example: https://godbolt.org/
how it works: https://xania.org/201609/how-compiler-explorer-runs-on-amazon
the repo: https://github.com/compiler-explorer/compiler-explorer




76.
Hmmnnn.
Risc is a good design:
https://itnext.io/yeah-risc-v-is-actually-a-good-design-1982d577c0eb

TODO:

- may be go through all the videos quoted by this person !
well researched article my man.

the comparison may seem naive, but these basic algos are executed multiple times behind the scenes.
this leads me to the #75.




77.
Chips Alliance:
https://chipsalliance.org/workgroups/

- rocket work-group seems the most interesting currently






78.
Another list of open cad tools relevant for chip design:
http://www.vlsiacademy.org/open-source-cad-tools.html




79.
Ajith processor IITB:
- it is based on SPARC as per the talk in #80
https://www.iitb.ac.in/en/research-highlight/welcome-ajit-%E2%80%98made-india%E2%80%99-microprocessor

toolchain:
https://github.com/adhuliya/ajit-toolchain




80.
Chip design process using open source tools:
This is one of the best talks for design process and the open source tools involved:

https://www.youtube.com/watch?v=OT9cecr9aFM

- https://github.com/kunalg123/vsdflow
the software used to demonstrate the design flow





TODOs
- one of the things I was not able to find from this talk:
Veda - software from IITG Prof.




81.
The open road project:
https://theopenroadproject.org/resources/
https://theopenroadproject.org/wp-content/uploads/2022/04/eri-2021-slides.pdf
https://github.com/The-OpenROAD-Project
https://github.com/The-OpenROAD-Project/OpenLane: RTL to GSD tool

- the default flow for efabless




82.
Great products line:
https://www.nordicsemi.com/Products

- thoughtfully designed

got introduced to it here, on the haskster.io instagram channel:
- https://www.nordicsemi.com/Products/Development-hardware/Nordic-Thingy-53




83.
CPU microarchitecture to get SPEED

https://www.youtube.com/watch?v=rglmJ6Xyj1c
TODO:
- watch after 20mins




- 1 word --> memory access !
mostly the entire talk is about faster memory access










82.
Good tool for converting verilog to FPGA conf. or physical hardware:

https://opencircuitdesign.com/qflow/







83.
Frontend and backend in chip design:
https://paginas.fe.up.pt/~ee07306/wp-content/uploads/2013/03/desing_flow_LuisGomes_v1.pdf

- the design process is very elaborately described:
it so well defined that I'd rather not loose it.
So here's a copy on my drive just in case:
https://drive.google.com/file/d/1WE2yY6CJ3-318jsFfAigrXJEWK59zCjP/view?usp=sharing





Work of a Frontend EngineerRTL Design/Coding
Synthesis
Functional Verification
DFT
Work of a Backend EngineerFloor Planning
Placement
Clock Tree Synthesis
STA
Physical Verification


Details:
http://verificationexcellence.in/vlsi-design-front-end-and-back-end/




Specification: This is the first stage in the design process where we define the important parameters of the system that has to be designed into a specification.
High level Design: In this stage, various details of the design architecture are defined. In this stage, details about the different functional blocks and the interface communication protocols between them etc. are defined.
Low level Design: This phase is also known as microarchitecture phase. In this phase lower level design details about each functional block implementation are designed. This can include details like modules, state machines, counters, MUXes, decoders, internal registers etc.
RTL coding: In RTL coding phase, the micro design is modelled in a Hardware Description Language like Verilog/VHDL, using synthesizable constructs of the language. Synthesizable constructs are used so that the RTL model can be input to a synthesis tool to map the design to actual gate level implementation later.
Functional Verification: Functional Verification is the process of verifying the functional characteristics of the design by generating different input stimulus and checking for correct behavior of the design implementation.
Logic Synthesis: Synthesis is the process in which a synthesis tool like design compiler takes in the RTL, target technology, and constraints as inputs and maps the RTL to target technology primitives. Functional equivalence checks are also done after synthesis to check for equivalence between the input RTL model and the output gate level model.
Placement and Routing: Gate-level netlist from the synthesis tool is taken and imported into place and route tool in the Verilog netlist format. All the gates and flip-flops are placed, Clock tree synthesis and reset is routed. After this each block is routed, output of the P&R tool is a GDS file, which is used by a foundry for fabricating the ASIC
Gate level Simulation: The Placement and Routing tool generates an SDF (Standard Delay File) that contains timing information of the gates. This is back annotated along with gate level netlist and some functional patterns are run to verify the design functionality. A static timing analysis tool like Prime time can also be used for performing static timing analysis checks
Fabrication: Once the gate level simulations verify the functional correctness of the gate level design after the Placement and Routing phase, then the design is ready for manufacturing. The final GDS file (a binary database file format which is the default industry standard for data exchange of integrated circuit or IC layout artwork) is normally send to a foundry which fabricates the silicon. Once fabricated, proper packaging is done and the chip is made ready for testing.
Post silicon Validation: Once the chip is back from fabrication, it needs to be put in a real test environment and tested before it can be used widely in the market. This phase involves testing in lab using real hardware boards and software/firmware that programs the chip. Since the speed of simulation with RTL is very slow compared to testing in lab with real silicon, there is always a possibility to find a bug in silicon validation and hence this is very important before qualifying the design for a market.

The set of above stages are roughly divided into two halves – the first half is known as Front end of VLSI design while the second half is referred to as Back end VLSI design.

Front End VLSI Design: All of the stages from Specification to Functional Verification are normally considered as part of Front end and engineers working on any of these are Front end VLSI design engineers.

Back End VLSI Design: All stages from Logic Synthesis till Fabrication are considered as back end and engineers working on any of these are considered as Back end VLSI design engineers.

Some job categories though have some vague distinction between front end vs back end:Post Silicon validation is normally a separate phase for product readiness. Some times engineers working on this have more interactions with front end design and verification engineers.
Emulation , FPGA design and PCB design are also not truly classified in this design flow.
Gate level simulation is mostly done my front end VLSI design engineers even though it is post synthesis
There are also separate job categories like Custom circuit design, Analog and Mixed signal circuit designs – which could be considered separate.







84.
Some new cores and chips:

SweRV - from western digital
https://github.com/chipsalliance/Cores-VeeR-EH1

Raven Chip -
SoC -->
https://opencircuitdesign.com/qflow/
https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless
https://www.hackster.io/ef/raven-risc-v-microcontroller-based-on-picorv32-core-f2f53d

picoRV32 -
core
- from the same team that maintains yosys
https://github.com/efabless/raven-picorv32






85.
This seems like a good fabrication facility:

https://efabless.com/startups

- probably 10mm2 is a very small space.
- but interesting process / proposition none-the-less

some knowledge base:
- https://efabless.com/knowledgebase


-

-x-x-x-
For tools
https://libresilicon.com/




86.
VLSI courses - for a kick start to a risc-v processor design

- generally looking at the courses has convinced me that - it is better to seek out youtube resources for specific topics and just start there.

- Good collection of what topics to cover and know:
https://www.vlsisystemdesign.com/basic_courses/



verilog - course free
https://www.chipverify.com/verilog/verilog-tutorial




- amazing free courses:
- channel:
https://www.youtube.com/c/VLSIAcademyhub
- physical design lecture series:
https://www.youtube.com/watch?v=kQYav5eZGeY&list=PL1h5a0eaDD3pimcMlzW15RpW02HPzIziL
- floor planning in physical design:
https://www.youtube.com/watch?v=5e-oOvP0Y-U&list=PL1h5a0eaDD3oPF3o6Rw3azZG-iXMOni3m
- static timing analysis lectures:
https://www.youtube.com/playlist?list=PL1h5a0eaDD3rMBdiRd8vyQDr8rRFbe4pG




paid courses:
- https://www.udemy.com/course/vsd-soc-design-of-the-picorv32-riscv-micro-processor/

- https://www.udemy.com/course/vsd-making-the-raven-chip-how-to-design-a-risc-v-soc/

- https://www.udemy.com/course/vlsi-academy/

- https://www.udemy.com/course/fpga-embedded-design-cpu/

- https://vlsideepdive.com/logic-synthesis-workshop-with-yosys/
- https://katchupindia.web.app/home - seems like a site with vlsideepdive material
- https://vlsideepdive.com/vlsi-design-flow-webinar-recordings-video-course/



- https://elearn.maven-silicon.com/risc-v
- https://elearn.maven-silicon.com/course/listing -- all courses from maven-silicon
- these guys have added their courses on udemy as well



the name is a bit odd:
https://vlsi-backend-adventure.com/index.html
- but seems like a great collection of short-notes about various important topics...
- seems like someone built it for their own quick revision :D






1000$
course
https://www.vlsisystemdesign.com/hdp/




87.
Speakers from Semicon India 2022




(planning to use the list to check out all the relevant companies, to get a lay of the land )
TODO: watch the events.. if posted online.



EVENT SPEAKERS

Here are some of our speakers




Speaker 1

Shri Ashwini Vaishnaw

Minister for Electronics & Information Technology, Railways and Communications




Speaker 5

Shri Rajeev Chandrasekhar

Minister of State for Electronics & Information Technology and Skill Development & Entrepreneurship




Speaker 4

Sanjay Mehrotra

President & CEO, Micron Technology




Speaker 4

Anirudh Devgan

President & CEO, Cadence Design Systems




Speaker 4

Randhir Thakur

President, Intel Foundry Services, Intel




Speaker 4

Vinod Dham

Founder Indo-Us Venture Partners




Speaker 3

Siva Sivaram

President, Western Digital




Speaker 2

Ajit Manocha

President & CEO, SEMI




Speaker 2

Prof. David Andrew Patterson

Prof. Emeritus, UC Berkley




Speaker 2

Prof. Arogyaswami Paulraj

Prof. Emeritus, Stanford




Speaker 2

Raja Koduri

Executive VP, Intel




Speaker 2

Lars Reger

CTO, NXP Semiconductors




Speaker 4

Prabu Raja

Senior Vice President Semiconductor Products Group, Applied Materials




Speaker 2

Sailesh Chittipeddi

Executive VP & GM IOT & Infrastructure, Renesas




Speaker 2

Rangesh Raghavan

Corporate VP & GM (India), LAM Research




Speaker 2

Walden Rhines

President & CEO, Cornami




Speaker 2

Jim Keller

CTO & President, Tenstorrent




Speaker 2

Matthew Grob

CTO, XCOM Labs




Speaker 2

Dr. Radha Nagarajan

Senior Vice President and Chief Technology Officer, Marvell Technology




Speaker 2

Prof. Kamakoti

Director, IIT Madras




Speaker 2

Prof. Umesh Mishra

UC Santa Barbara




Speaker 2

Prof. Rao Tummala

Georgia Tech




Speaker 2

Dinesh Ramanathan

CEO, NextGen Power Systems




Speaker 2

Primit Parikh

President, Transphorm




Speaker 2

Nivruti Rai

Country Head, Intel India




Speaker 2

Barun Dutta

Chief Scientist, IMEC




Speaker 4

Sri Samavedam

Senior Vice-President, CMOS Technologies, IMEC




Speaker 2

Raja Manickam

CEO, Tata Electroics (OSAT)




Speaker 2

Jaya Jagdish

Country Head, AMD India




Speaker 2

Akarsh Hebbar

MD, Avanstrate




Speaker 2

Parag Naik

CEO, SAANKHYA Labs




Speaker 2

Rama Divakaruni

Distinguished Engineer, IBM Research




Speaker 2

Ganapathy Subramaniam

Partner, Celesta Capital




Speaker 2

Vivek Sharma

MD, ST Microelectronics India




Speaker 4

Srinivas Satya

President & Managing Director Applied Materials India




Speaker 4

Suraj Rengarajan

CTO & Managing Director, Applied Materials India




Speaker 4

Dr. Kumar N. Sivarajan

Co-founder & CTO, Tejas Network




Speaker 4

Sid Sheth

Founder & CEO, d-Matrix




Speaker 4

Sajiv Dalal

Executive Vice President, TSMC




Speaker 3

K. Rajaraman

Secretary DoT & Secretary (Additional Charge) MeitY






88.
Readiness Analysis for open source processors:
https://semiengineering.com/open-source-processors-fact-or-fiction/

TODO

RISC_V - status of the landscape as of 2017
https://riscv.org/wp-content/uploads/2017/02/riscv_fosdem17.pdf


89.
1100 cores:
https://www.hpcwire.com/2020/12/08/esperanto-unveils-ml-chip-with-nearly-1100-risc-v-cores/

take aways:
- open-source Glacier Point card -- TODO
-
"
explaining that the chip’s tile-based design made it easy “scale up to more thousands of cores or scale down to hundreds of cores,” serving needs “from hyperscale datacenters to edge AI and everything in-between.”
"

90.
This one is focused on Server Hardware:
https://www.opencompute.org/wiki/Main_Page




91.
More open computing hardware:
https://en.wikipedia.org/wiki/List_of_open-source_computing_hardware

- TODO

92.
good talk about the mor1kx: (also filed with the or1k main point)
https://www.youtube.com/watch?v=uYRWFN-ii68
mor1k:
- improvements made
- 3-stage and 6-stage configurable
- test suit
- instruction level logging
- multi-core also now supported - with addition of atomic transactions




93.
Analysis of the current RISC landscape:
https://www.zdnet.com/article/risc-v-opens-up-processor-design/



"
Under the hood, though, Intel's chips were remarkably RISC-like, with the CISC features translated into RISC instructions internally. The mobile market, which evolved independently of Windows, soon settled on ARM chips, which used RISC design to be far more power-efficient. RISC can be said to have won the case across the board.
"

94.
One more:
https://www.oracle.com/servers/technologies/opensparc-overview.html






95.
Open source:
http://parallel.princeton.edu/openpiton/

"
OpenPiton is designed to be highly configurable, including core count, cache sizes, and NoC topology, enabling it to adapt to different use cases




Written in Verilog HDL
Scalable up to 1/2 Billion Cores
Configurable core and uncore
Includes synthesis and back-end flows for ASIC and FPGA
Support for multiple target FPGA boards
Runs full stack multi-user Debian Linux
Multiple I/O device options, including Ethernet

"
https://github.com/PrincetonUniversity/openpiton
- this is a SPARC architecture project
- recently supporting the Ariane RISC-V project
- may be the micro-architecture can be used as an inspiration on the design, if using the project itself cannot be used.

96.
This is another collection of cores
https://opencores.org/projects

-- all the cores seen so far here... are all available / registered on the open cores wiki

97.
https://openrisc.io/
This seems to be more on the software and emulation side


But finally this seems like the place to start with for say building an SoC
https://openrisc.io/soc


This seems to the default processor of choice:
https://openrisc.io/implementations.html#mor1kx
https://github.com/openrisc/orpsoc-cores




https://openrisc.io/
the project has:
- javascript emulator of open risc 1000 running linux:
https://github.com/s-macke/jor1k/
(absolutely amazing and bonkers if you ask me)

- processor cores (listed below)

- system simulators:
- https://github.com/openrisc/or1ksim
- can be done on the qemu for:
-- visualisations
-- or a machine emulator
How to run a or1k with QEMU:
- https://wiki.qemu.org/Documentation/Platforms/OpenRISC
- man page: https://helpmanual.io/help/qemu-or1k/



- System on Chips (SoCs) - mentioned below
- OS - can run linux and RTEMS
-


architecture:
https://openrisc.io/architecture



https://openrisc.io/soc
List of a few SoC generators


fusesoc is a new SoC generator that not only supports OpenRISC. It also manages the available peripheral cores and allows you to easily configure and generate your system-on-chip.


minsoc is a minimal OpenRISC-based system-on-chip, that is easy to configure and implement, but still uses the OR1200 processor implementation.


OpTiMSoC is a flexible multicore system-on-chip that is based on a network-on-chip and connects a configurable number of OpenRISC (mor1kx) processors to arbitrarily large platforms.
- can boot linux (I am guessing on a simulator / fpga; this is great for a complex chip)
- the linux loading process: https://www.optimsoc.org/blog/2018/12/19/linux.html
- system architecture for booting linux: https://www.youtube.com/watch?v=Wp_2eORlWek
- development process talk by one of the developers: https://www.youtube.com/watch?v=uYRWFN-ii68


MiSoC is a SoC generator using the Python based Migen which can use the mor1k processor. Both high performance and optimized for small FPGA footprint, it supports a large number of development boards out the box.
- repo: https://github.com/m-labs/misoc
-


-x-x-x-


LiteX - focused on FPGA cores
frequently used abbreviation:
orbis 32 /64 - Open risc basic instruction set

Tutorials to go with these:
https://openrisc.io/tutorials.html



Toolchains
A few toolchains are generally supported. A C library is an essential part of your toolchain as it provides you the basic features. The following toolchains with different C libraries are available:

- newlib is a small library mainly used for baremetal usage. We also maintain a port of it for the baremetal toolchain or1k-elf-gcc

- musl is a C library with a strong emphasis on being light-weight and correctness. The Linux toolchain is or1k-linux-musl-gcc.

- uClibc-ng a reboot of the uClibc project, is a similar small library and primarily used for Linux applications. The Linux toolchain is or1k-linux-uclibc-gcc.

- glibc is a fully featured C Library for Linux. The Linux toolchain is or1k-linux-gnu-gcc.




Applications
Cross compiling applications to your OpenRISC embedded target and packaging them up into a root filesystem image could be tedious. There are a few options to smooth the process:

- Buildroot has support for building applications using the uClibc-ng toolchain.

- OpenADK from the maintainers of uClibc-ng has support for building using both uClibc-ng and musl toolchains.




98.
https://www.crowdsupply.com/sifive/hifive-unmatched
This seems to be the top of the line right now..

https://www.crowdsupply.com/sifive/hifive-unmatched
Complete evaluation board + chip @ ~50K INR


and seems to be running linux comfortably.

99.
https://riscv.org/

Available boards:
https://riscv.org/exchange/

Cores and SoC
https://riscv.org/exchange/cores-socs/

Available softwares
https://riscv.org/exchange/software/

- I like that at-least this ecosystem gets richer as you come to layers of higher abstraction.







100.
IITM Shakti processors:
https://shakti.org.in/processors.html

I am most interested in:
M-class --> mobile
S-class. --> desktop
H-class --> parallel workloads


H+M+S combo will be the future







Progress:
I-class --> https://shakti.org.in/docs/shaktiweek-i-class.pdf
some work left

C-class and E-class
desigs available:
https://gitlab.com/shaktiproject/cores
can be tried out on an FPGA:
https://shakti.org.in/ideate-and-build.html
tutorial on writing, compiling, building, running ASM / c code on spike / fpga emulator:
https://shakti.org.in/learn_with_shakti/intro.html




-x-x-x-
RISC-V based SSD controller
https://manualzz.com/doc/25695698/lightstor-storage








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